1. Field of the Invention
The present invention relates to a layout input apparatus, a layout input method, a layout verification apparatus and a layout verification method.
2. Description of the Related Art
In recent years, the degree of integration of semiconductor integrated circuits is increasing, and their operation speed is becoming higher. Under this circumstance, various large-scale systems are being realized by a semiconductor integrated circuit formed on a single chip, which greatly contributes to the miniaturization and decrease in cost of such systems.
However, in order to produce a semiconductor integrated circuit whose minimum size is reduced to a quarter micron or less, significant capital investment is required. Furthermore, it is becoming difficult to enhance production yield with the increase in chip area and high integration of a semiconductor integrated circuit. Therefore, it may cost lower to realize a large-scale system by combining a plurality of relatively large semiconductor integrated circuits produced by a conventional process than to realize a large-scale system on a single chip.
A mounting technique as shown in FIGS. 34A through 34D has been proposed for the purpose of reducing the production cost and mounting area of a semiconductor integrated circuit. According to this mounting technique, a semiconductor chip with a first LSI formed thereon (first LSI chip) and a semiconductor chip with a second LSI formed thereon (second LSI chip), as shown in FIG. 34A, are mounted in a single package in such a manner that they are superposed on top of the other. For example, a semiconductor integrated circuit chip with a central processing unit (CPU) formed thereon is used as the first LSI chip, and a semiconductor integrated circuit chip with a static RAM (SRAM) is used as the second LSI chip.
Conventional semiconductor integrated circuits are composed of a number of semiconductor devices formed on one principal surface of a semiconductor substrate (semiconductor chip) and wirings connecting the devices to each other. According to the Flip & Stack mounting technique, two semiconductor chips are placed in such a manner that their surfaces on which semiconductor integrated circuits are formed face each other, as shown in FIGS. 34B through 34D. Terminal pins (not shown) of a package are electrically connected through bonding wires to a bonding pad provided on the periphery of the first LSI chip. Input/output (I/O) terminals of the second LSI chip are connected to I/O terminals for Flip & Stack mounting provided on the first LSI chip. Such a connection requires the first LSI chip and the second LSI chip to be provided with electrical connecting portions which have a "mirror inversion" relationship, as shown in FIG. 34A.
As described above, according to the conventional Flip & Stack mounting technique, two semiconductor integrated circuits which are different in function and use, such as a CPU and an SRAM, are used as the first and second LSIs. The layouts of these two semiconductor integrated circuits are independently designed by a conventional layout input method, after the coordinates of the connecting portions which have a mirror inversion relationship are defined.
However, the conventional layout input method does not allow the layouts of two LSIs to be designed simultaneously. This makes it difficult to determine optimum layouts, resulting in an increase in the time required for designing layouts. In addition, the layout verification is required to be conducted independently with respect to two LSIs. Therefore, the number of steps of forming net lists for an individual LSI increases. Furthermore, the connection between two LSIs is manually checked, which increases verification time and decreases reliability.